From 1521172b9d603df03751b25a85b2bd6a74bdf3c7 Mon Sep 17 00:00:00 2001 From: Daniel Han Date: Fri, 3 Jul 2026 19:18:54 +0000 Subject: [PATCH] Show the compile control for SDXL in the Train settings The compile select was nested inside the DiT-only branch of the precision area, so supports_compile=true for sdxl never rendered it. Lift it out of the ternary: the precision selects stay family-specific, the compile control follows supports_compile. Verified with a live Playwright pass (mxfp8 listed for DiT families on sm100, compile select present for SDXL, DiT precision selector still hidden for SDXL). --- .../images/train/diffusion-train-panel.tsx | 90 +++++++++---------- 1 file changed, 44 insertions(+), 46 deletions(-) diff --git a/studio/frontend/src/features/images/train/diffusion-train-panel.tsx b/studio/frontend/src/features/images/train/diffusion-train-panel.tsx index 6ef3599e34..d3f089a42c 100644 --- a/studio/frontend/src/features/images/train/diffusion-train-panel.tsx +++ b/studio/frontend/src/features/images/train/diffusion-train-panel.tsx @@ -812,52 +812,29 @@ export function DiffusionTrainPanel({ {isDiT ? ( - <> -
- - -

- How the frozen base weights are quantised. nf4 (4-bit) uses the least VRAM; - bf16 is fastest but needs the most. Auto picks this family's recommended - mode. -

-
- {supportsCompile && ( -
- - -

- torch.compile the transformer. Adds a one-time warmup, then speeds up each - step. -

-
- )} - +
+ + +

+ How the frozen base weights are quantised. nf4 (4-bit) uses the least VRAM; + bf16 is fastest but needs the most. Auto picks this family's recommended + mode. +

+
) : (
@@ -876,6 +853,27 @@ export function DiffusionTrainPanel({

)} + {supportsCompile && ( +
+ + +

+ torch.compile the transformer blocks. Adds a one-time warmup, then speeds up + each step. +

+
+ )} );